1. Field of the Invention
The present invention relates to a circuit for employing pulse signals in a reverse phase to raise a voltage until it is equal to or higher than a predetermined power voltage, or to drop a voltage until it is equal to or lower than the predetermined power voltage, such as ground. In particular, the present invention pertains to a voltage booster circuit or a voltage drop circuit, the booster level or the drop level of which can be changed as needed.
2. Related Art
In a semiconductor device, a voltage booster circuit and a voltage drop circuit are employed to generate a voltage higher than a power source voltage and to generate a voltage lower than a power source voltage, such as ground. In a nonvolatile memory used for flash memory, for example, a voltage booster circuit is used for a write circuit and a voltage drop circuit is used for an erasing circuit, and a voltage that is raised or dropped by such a circuit is applied to a word line and a bit line, to which a memory cell is connected.
FIG. 18 is a diagram illustrating a common voltage booster circuit. In this voltage booster circuit, N MOS transistors Q11, Q12, Q13 and Q14 which are connected as a diode are connected in series, and capacitors C11, C12, C13 and C14 are connected to their connection points. Power source Vcc is connected to the drain terminal of the transistor Q11 which is connected as a diode at the first stage, and output OUT is connected to the source terminal of the transistor Q14 which is connected as a diode at the last stage. As is shown in FIG. 18, clock pulses having opposite phases, CLK and CLKB, are alternately applied to the capacitors C, and through the voltage raising operation of the capacitors C, electric charges are transferred, progressively, from individual nodes N1, N2, N3 and N4 to their adjacent nodes toward the last stage. As a result, a voltage obtained by raising about five times the power source voltage Vcc that is the amplitude of a clock pulse is generated at the output OUT.
FIG. 19 is a diagram illustrating a common voltage drop circuit. In this voltage drop circuit, P-MOS transistors Q21, Q22, Q23 and Q24 which are connected as a diode are connected in series, and capacitors C21, C22, C23 and C24 are connected to their connection points. Power source ground GND is connected to the drain terminal of the transistor Q21, which is connected as a diode at the first stage, and output OUT is connected to the source terminal of the transistor Q24, which is connected as a diode at the last stage. As is shown in FIG. 19, clock pulses having opposite phases, CLK and CLKB, are alternately applied to the capacitors C, and through the voltage drop operation of the capacitors C, electric charges are transferred, progressively, from nodes P1, P2, P3 and P4 to their adjacent nodes toward the first stage. As a result, a negative voltage obtained by dropping by about four times the power source voltage Vcc that is the amplitude of the clock pulse is generated at the output OUT.
As is described above, when clock pulses in opposite phases are respectively supplied to odd numbered capacitors and even numbered capacitors, a voltage can be generated that is obtained by raising or dropping the power voltage integer times. In addition, when more circuits constituted by transistors connected as a diode and capacitors are provided, either a higher or a lower voltage can be generated.
When, for example, both 3 V and 5 V are employed as power voltages to be supplied to the semiconductor device, for a voltage booster circuit or a voltage drop circuit designed for 3 V, a voltage higher than a designed voltage may be applied to the nodes when the power voltage of 5 V is applied, and transistors and capacitors may be damaged. Generally, the generation of a desired voltage that does not depend on a supplied power voltage is required. Even when a high power voltage is applied, therefore, it is not required that an accompanying high or low voltage be generated.
Even in a case where a plurality of voltages are not applicable as the power voltage, if a power voltage to be applied is raised, the same problem arises as is described above, that devices in the voltage booster circuit or the voltage drop circuit will be damaged.